description the acpl- w454/p454 is similar to avago technologies other high speed transistor output optocouplers, but with shorter propagation delays and higher ctr. the acpl- w454/p454 also has a guaranteed propagation delay difference (t plh - t phl ). these features make the acpl- w454/p454 an excellent solution to ipm inverter dead time and other switching problems. the acpl-w454/p454 ctr, propagation delays, and cmr are specified both for ttl load and drive conditions and for ipm (intelligent power module) load and drive conditions. specifications and typical performance plots for both ttl and ipm conditions are provided for ease of application. this diode-transistor optocoupler uses an insulating layer between the light emitting diode and an integrated photo detector to provide electrical insulation between input and output. separate connections for the photodiode bias and output transistor collector increase the speed up to a hundred times over that of a conventional phototransistor coupler by reducing the base-collector capacitance. functional diagram features package clearance/creepage at 8mm (acpl-w454) function compatible with hcpl-4504 surface mountable in 6-pin stretched so6 short propagation delays for ttl and ipm applications very high common mode transient immunity: guaran- teed 15 kv/ s at v cm = 1500 v high ctr: >25% at 25c guaranteed specifications for common ipm applica- tions ttl compatible guaranteed ac and dc performance over temperature: 0c to 70c open collector output safety approval ul recognized 3750 vrms for 1 minute (5000 vrms for 1 minute under acpl-w454 devices) per ul1577 csa approved iec/en/din en 60747-5-2 approved with v iorm = 1140 vpeak (acpl-w454) and v iorm = 891 vpeak (acpl-p454) for option 060. applications inverter circuits and intelligent power module (ipm) in- terfacing C shorter propagation delays and guaranteed (t plh - t phl ) specifications. high speed logic ground isolation - ttl/ttl, ttl/lttl, ttl/cmos, ttl/lsttl line receivers - high common mode transient immunity (>15 kv/ s for a ttl load/drive) and low input-output capacitance (0.6 pf). replace pulse transformers - save board space and weight analog signal ground isolation - integrated photo detector provides improved linearity over phototransistors 1 2 3 6 5 4 anode nc cathode vcc v o gnd a 0.1 f bypass capacitor between pins 4 and 6 is recommended. truth table led on off v o low high acpl-p454 and acpl-w454 high cmr high speed optocoupler data sheet schematic lead (pb) free rohs 6 fully compliant ro h s 6 f u lly co m p l i an t optio ns ava i labl e ; -xxxe de n ote s a l e a d -f ree product i f shield 6 5 4 gnd v cc 1 3 v o i cc v f i o anode cathode + e caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd.
2 package outline drawings acpl-w454 (stretched so6, 8mm clearance) ordering information acpl-p454 and acpl-w454 are ul recognized with 3750 vrms (5000 vrms under acpl-w454) for 1 minute per ul1577 and are approved under csa component accep tance notice #5, file ca 88324. part number option package surface mount tape & reel iec/en/din en 60747-5-2 quantity rohs compliant acpl-p454 acpl-w454 -000e stretched so-6 x 100 per tube -500e x x 1000 per reel -060e x x 100 per tube -560e x x x 1000 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: acpl-p454-560e to order product of stretched so-6 package in tape and reel packaging with iec/en/din en 60747- 5-2 safety approval in rohs compliant. example 2: acpl-p454-000e to order product of stretched so-6 package in tube packaging and rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. 1 2 3 4 5 6 0.38 0.127 [.015 .005] 1.27 [.050] bsg 4.580 +0.254 0 .180 +.010 - .000 0.76 [.030] 12.65 [.498] 1.91 [.075] 1.590 0.127 [.063 .005] 3.180 0.127 [.125 .005] 6.807 +0.127 0 .268 +.005 - .000 0.45 [.018] 0.750 0.250 [0.0295 0.010] 0.20 0.10 [.008 .004] 11.50 0.250 [.453 .010] 7 45 7 land pattern recommendation dimensions in millimeters [inches] coplanarity = 0.1mm [0.004 inches]
3 acpl-p454 (stretched so6, 7mm clearance) recommended pb-free ir profile recommended reflow condition as per jedec standard, j-std-020 (latest revision). non-halide flux should be used. regulatory information the acpl-w454/p454 are approved by the following organizations: iec/en/din en 60747-5-2 (option 060 only) approval under: iec 60747-5-2 :1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884 teil 2):2003-01 ul - approval under ul 1577, component recognition pro- gram up to v iso = 3750 v rms (5000vrms for acpl-w454). file e55361. csa - approval under csa component acceptance notice #5, file ca 88324. 0.38 0.127 [.015 .005] 1.27 [.050] bsg 4.580 +0.254 0 .180 +.010 - .000 0.45 [.018] 7.62 [.300] 6.81 [.268] [.063 .005] 1.590 0.127 a 9.7 0.250 [.382 .010] 3.180 0.127 7.00 45.00 7.00 7.00 7.00 [.040 .010] 1 .0.250 0.20 0.10 [.008 .004] 0.20 [.008] 2.16 [.085] 10.7 [.421] [.125 .005] land pattern recommendation dimensions in millimeters [inches] coplanarity = 0.1mm [0.004 inches]
4 insulation related specifications parameter symbol w454 p454 units conditions value value min external air gap (clearance) l(io1) 8 7 mm measured from input terminals to output terminals min. external tracking path (creepage) l(io2) 8 8 mm measured from input terminals to output terminals min. internal plastic gap (clearance) 0.08 0.08 mm through insulation distance conductor to conductor tracking resistance cti 175 175 v din iec 112/vde 0303 part 1 isolation group (per din vde 0109) iiia material group din vde 0109 iec/en/din en 60747-5-2 insulation related characteristics (option 060 only) description symbol acpl-w454 acpl-p454 units installation classification per din vde 0110/1.89, table 1 for rated mains voltage 150 vrms for rated mains voltage 300 vrms for rated mains voltage 450 vrms for rated mains voltage 600 vrms for rated mains voltage 1000 vrms i-iv i-iv i-iii i-iii i-ii i-iv i-iv i-iii i-iii climatic classification 55/100/21 55/100/21 pollution degree (din vde 0110/1.89) 2 2 maximum working insulation voltage v iorm 1140 891 v peak input to output test voltage, method b* v iorm x 1.875 = v pr , 100% production test with t m = 1 sec partial discharge < 5 pc, v pr 2137 1670 v peak input to output test voltage, method a* v iorm x 1.5 = v pr , type and sample test, t m = 60 sec, partial discharge < 5 pc v pr 1710 1336 v peak highest allowable overvoltage* (transient overvoltage, t ini = 10 sec) v iotm 8000 8000 v peak safety limiting values (maximum values allowed in the event of a failure) case temperature input current output power t s i s,input p s,output 175 230 600 175 230 600 c ma mw insulation resistance at t s , v io = 500 v r s 10 9 10 9 * refer to the optocoupler section of the designers catalog, under regulatory information (iec/en/din en 60747-5-2) for a deta iled description of method a and method b partial discharge test profiles.
5 absolute maximum ratings storage temperature -55c to +125c operating temperature -55c to +100c average input current - i f 25 ma [1] peak input current - i f 50 ma [2] (50% duty cycle, 1 ms pulse width) peak transient input current - i f 1.0 a ( 1 ms pulse width, 300 pps) reverse input voltage - v r (pin3-1) 5 v input power dissipation 45 mw [3] average output current - i o (pin 5) 8 ma peak output current 16 ma output voltage - v o (pin 5-4) -0.5 v to 20 v supply voltage - v cc (pin 6-4) -0.5 v to 30 v output power dissipation 100 mw [4] solder reflow temperature profile see package outline drawings section dc electrical specifications over recommended temperature (t a = 0c to 70c) unless otherwise specified. parameter symbol min typ.* max. units test conditions fig. note current transfer ratio ctr 25 32 60 % t a = 25c v o = 0.4 v i f = 16 ma v cc = 4.5 v 1, 2, 4 5 21 34 v o = 0.5 v current transfer ratio ctr 26 35 65 % t a = 25c v o = 0.4 v i f = 12 ma v cc = 4.5 v 5 22 37 v o = 0.5 v logic low output voltage v ol 0.2 0.4 v t a = 25c i o = 3.0 ma i f = 16 ma v cc = 4.5 v 1 0.2 0.5 i o = 2.4 ma logic high output current i oh 0.003 0.5 a t a = 25c v o = v cc = 5.5 v i f = 0 ma 5 0.01 1 t a = 25c v o = v cc = 15.0 v 50 logic low supply current i ccl 50 200 a i f = 16 ma, v cc = 15 v v o = open, 11 logic high supply current i cch 0.02 1 a t a = 25c i f = 16 ma, v o = open, v cc = 15 v 11 0.02 2 input forward voltage v f 1.5 1.7 v t a = 25c i f = 16 ma 3 1.5 1.8 input reverse breakdown voltage bv r 5v i r = 10 a temperature coefficient of for- ward voltage v f / t a -1.6 mv/c i f = 16 ma input capacitance c in 60 pf f = 1 mhz, v f = 0 *all typicals at t a = 25c.
6 switching specifications over recommended temperature (t a = 0c to 70c) unless otherwise specified parameter symbol min. typ.* max. units test conditions fig. note propagation delay time to logic low at output t phl 0.2 0.3 s t a = 25c pulse: f = 20 khz, duty cycle = 10% i f = 16 ma, v cc = 5.0 v r l = 1.9 k , c l = 15 pf v thhl = 1.5 v 6,8,9 9 0.2 0.5 0.2 0.5 0.7 t a = 25c pulse: f = 10 khz, duty cycle = 50% i f = 12 ma, v cc = 15.0 v r l = 20 k , c l = 100 pf v thhl = 1.5 v 6, 10-14 10 0.1 0.5 1.0 propagation delay time to logic high at output t plh 0.3 0.5 s t a = 25c pulse: f = 20 khz, duty cycle = 10% i f = 16 ma, v cc = 5.0 v r l = 1.9 k , c l = 15 pf v thhl = 1.5 v 6,8,9 9 0.3 0.7 0.3 0.8 1.1 t a = 25c pulse: f = 10 khz, duty cycle = 50% i f = 12 ma, v cc = 15.0 v r l = 20 k , c l = 100 pf v thhl = 2.0 v 6, 10-14 10 0.2 0.8 1.4 propagation delay difference between any 2 parts t plh - t phl -0.4 0.3 0.9 s t a = 25c pulse: f = 10 khz, duty cycle = 50% i f = 12 ma, v cc = 15.0 v r l = 20 k , c l = 100 pf v thhl = 1.5 v v thlh = 2.0v 6, 10-14 13 -0.7 0.3 1.3 s common mode transient immu- nity at logic high level output |cm h |1530 kv/ s t a = 25c v cc = 5.0 v, r l = 1.9 k c l = 15 pf, i f = 0 ma v cm = 1500 v p-p 7 7,9 15 30 t a = 25c v cc = 15.0 v, r l = 20 k c l = 100 pf, i f = 0 ma v cm = 1500 v p-p 7 8,10 common mode transient immu- nity at logic low level output |cm l |1530 kv/ s t a = 25c v cc = 5.0 v, r l = 1.9 k c l = 15 pf, i f = 16 ma v cm = 1500 v p-p 7 7,9 15 30 t a = 25c v cc = 15.0 v, r l = 20 k c l = 100 pf, i f = 12 ma v cm = 1500 v p-p 7 8,10 15 30 t a = 25c v cc = 15.0 v, r l = 20 k c l = 100 pf, i f = 16 ma v cm = 1500 v p-p 7 8,10 *all typicals at t a = 25c.
7 figure 1. dc and pulsed transfer characteristics. package characteristics over recommended temperature (t a = 0c to 70c) unless otherwise specified. all typicals at t a = 25c. parameter symbol min. typ. max. units test conditions fig. note input-output momentary withstand voltage* v iso 3750 vrms rh 50%, t = 1 min, t a = 25c 6,12 5000 (for acpl-w454) input-output resistance r i-o 10 12 v i-o = 500 vdc 6 input-output capacitance c i-o 0.6 pf f = 1 mhz; v i-o = 0 vdc 6 * the input-output momentary withstand voltage is a dielectric v oltage rating that should not be interpreted as an input-output c ontinuous voltage rating. for the continuous voltage rating refer to the iec/en/din en 60747-5-2 insulation characteristics table (if applicable) . notes: 1. derate linearly above 70c free-air temperature at a rate of 0.8 ma/c. 2. derate linearly above 70c free-air temperature at a rate of 1.6ma/c. 3. derate linearly above 70c free-air temperature at a rate of 0.9 mw/c. 4. derate linearly above 70c free-air temperature at a rate of 2.0 mw/c. 5. current transfer ratio in percent is defined as the ratio of output collector current (i o ), to the forward led input current (i f ), times 100. 6. device considered a two-terminal device: pins 1 and 3 shorted together and pins 4, 5 and 6 shorted together. 7. under ttl load and drive conditions: common mode transient immunity in a logic high level is the maximum tolerable (positive ) dv cm /dt on the leading edge of the common mode pulse, v cm , to assure that the output will remain in a logic high state (i.e., v o > 2.0 v). common mode transient immunity in a logic low level is the maximum tolerable (negative) dv cm /dt on the trailing edge of the common mode pulse signal, v cm, to assure that the output will remain in a logic low state (i.e., vo < 0.8 v). 8. under ipm (intelligent power module) load and led drive conditions: common mode transient immunity in a logic high level is the maximum tolerable dv cm /dt on the leading edge of the common mode pulse, vcm, to assure that the output will remain in a logic high state (i.e., v o > 3.0 v). common mode transient immunity in a logic low level is the maximum tolerable dv cm /dt on the trailing edge of the common mode pulse signal,v cm , to assure that the output will remain in a logic low state (i.e., v o < 1.0 v). 9. the 1.9 k load represents 1 ttl unit load of 1.6 ma and the 5.6 k pull-up resistor. 10. the r l = 20 k , c l = 100 pf load represents an ipm (intelligent power mode) load. 11. use of a 0.1 f bypass capacitor connected between pins 4 and 6 is recommended. 12. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 4500 v rms for 1 second (leakage detection current limit, i i-o 5 a); each optocoupler under acpl-w454 is proof tested by applying an insulation test voltage 6000 v rms for 1 second (leak- age detection current limit, i i-o 5 a). 13. the difference between t plh and t phl , between any two acpl-w454/p454 parts under the same test condition. (see power inverter dead time and propagation delay specifications section). figure 2. current transfer ratio vs. input current . figure 3. input current vs. forward voltage. 0 10 20 v o - output voltage - v i o - output current - ma 10 5 0 t = 25 ?c v = 5.0 v a cc 40 ma 35 ma 30 ma 25 ma 20 ma 15 ma 10 ma i = 5 ma f i f - input current - ma normalized current transfer ratio 1.5 1.0 0.5 0.0 2 4 6 8 10 12 14 16 18 0 20 22 24 26 i f = 16 ma v o = 0.4 v v cc = 5.0 v t a = 25 ?c normalized v f - forward voltage - volts 100 10 0.1 0.01 1.1 1.2 1.3 1.4 i f - forward current - ma 1.6 1.5 1.0 0.001 1000 i f v f + t = 25?c a -
8 figure 6. switching test circuit. v o pulse gen. z o = 50 t r = 5 ns i f monitor i f 0.1f r l c l 100 0 t phl t plh v o i f v ol v thhl v thlh v cc 1 3 6 5 4 acpl-w454/p454 v cc 2 v o 0.1f r l a b pulse gen. v cm + v ff c l v cc - 1 3 6 5 4 v o v ol v o 0 v 10% 90% 90% 10% switch at a: i = 0 ma f switch at b: i = 12 ma, 16 ma f v cm t r t f v cc 10 v i f acpl-w454/p454 2 figure 7. test circuit for transient immunity and typical waveforms. figure 4. current transfer ratio vs. temperature. figure 5. logic high output current vs. tempera- ture. t a - temperature - ?c normalized current transfer ratio 1.0 0.8 0.6 1.1 0.7 0.9 -40 -20 0 20 40 60 80 100 120 -60 i f = 16 ma v o = 0.4 v v cc = 5.0 v t a = 25 ?c normalized t a - temperature - ?c i oh - logic high output current - na 10 4 10 3 10 2 10 1 10 0 10 -1 10 -2 -40 -20 0 20 40 60 80 100 120 -60 i f = 0 ma v o = v cc = 5.0 v
for product i nf or ma tio n an d a co m plete li s t o f di s tri b utor s , ple as e go to our we b s ite: www.avagotech.com a va go, a va go tech n ologie s , an d the a logo a re tr a de ma rk s o f a va go tech n ologie s i n the u n ited st a te s an d other cou n trie s . d a t a s u b ject to ch an ge. cop y right ? 2005 - 2010 a va go tech n ologie s . all right s re s er v ed. o bs olete s av01 - 0253en av02 - 1307en - augu s t 4, 2010 figure 11. propagation delay time vs. tempera- ture. figure 12. propagation delay time vs. load re- sistance. figure 13. propagation delay time vs. load capacitance. figure 14. propagation delay time vs. supply voltage. t a - temperature - ?c tp - propagation delay - s 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 -40 -20 0 20 40 60 80 100 120 -60 v cc = 15.0 v r l = 20 k c l = 100 pf v thhl = 1.5 v v thlh = 2.0 v t plh t phl i f = 10 ma i f = 16 ma 50% duty cycle r l - load resistance - k t p - propagation delay - s 1.6 1.4 1.2 1.0 0.6 0.2 0.0 5 101520 2530354045 0 v cc = 15.0 v t a = 25 ?c c l = 100 pf v thhl = 1.5 v v thlh = 2.0 v 50 t plh t phl 1.8 0.4 0.8 i f = 10 ma i f = 16 ma 50% duty cycle c l - load capacitance - pf t p - propagation delay - s 2.0 1.5 0.5 0.0 200 400 600 800 0 v cc = 15.0 v t a = 25 ?c r l = 20 k v thhl = 1.5 v v thlh = 2.0 v 1000 t plh t phl 2.5 3.0 3.5 1.0 i f = 10 ma i f = 16 ma 50% duty cycle v cc - supply voltage - v tp - propagation delay - s 0.9 0.8 0.6 0.2 11 12 13 14 15 16 17 18 19 10 20 1.0 1.1 1.2 0.7 t a = 25 ?c r l = 20 k c l = 100 pf v v 0.5 0.4 0.3 t plh t phl i f = 10 ma i f = 16 ma 50% duty cycle thhl = 1.5 v = 2.0 v thlh t a - temperature - ?c tp - propagation delay - s 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 -40 -20 0 20 40 60 80 100 120 -60 v cc = 5.0 v r l = 1.9 k c l = 15 pf v thhl t plh t phl i f = 10 ma i f = 16 ma = v thlh = 1.5 v 10% duty cycle r l - load resistance - k tp - propagation delay - s 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2 4 6 8 10 12 14 16 18 0 20 t phl v cc = 5.0 v t a = 25 ?c c l = 15 pf v = v = 1.5 v i f = 10 ma i f = 16 ma t plh 10% duty cycle thhl thlh r l - load resistance - k tp - propagation delay - s 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2 4 6 8 10 12 14 16 18 0 20 1.6 1.8 2.0 2.2 2.4 2.6 v cc = 5.0 v t a = 25 ?c c l = 100 pf v thhl = 1.5 v v thlh = 2.0 v i f = 10 ma i f = 16 ma t plh t phl 50% duty cycle figure 8. propagation delay time vs. tempera- ture. figure 9. propagation delay time vs. load resis- tance. figure 10. propagation delay time vs. load resistance.
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